序列检测器VHDL程序代码.docVIP

序列检测器VHDL程序代码 序列检测器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity detect110 is port(clk,D_in:in std_logic; en:in std_logic; D_out:out std_logic ); end entity; architecture behav of detect110 is type state is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11); signal n:state; signal p:state; begin process(clk) begin if clk’event and clk=‘1’ then n if(D_in=‘1’) then p if(D_in=‘1’) then p if(D_in=‘1’) then p if(D_in=‘1’) then p if(D_in=‘1’) then p if(D_in=‘1’) then p if(D_in=‘1’) then p if(D_in=‘0’) then p if(D_in=‘1’) then p if(D_in=‘1’) then p if(D_in=‘1’) then p if(D_in=‘0’) then pnull; end case; else D_out=‘0’; end if; end process; end behav; 交通灯 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity light is port(clk: in std_logic; dclk1:out std_logic; ra:out std_logic; ga:out std_logic; ya:out std_logic; rb:out std_logic; gb:out std_logic; yb:out std_logic ); end light; architecture Behavioral of light is signal clk1: std_logic := ‘1’; signal q: integer range 0 to=0; begin dclk1=clk1; t1: process(clk) begin if clk’event and clk=‘1’ then if q=129 then q=0;clk1=not clk1; else q=q+1; end if ; end if; end process; t3: process(q) begin i