操作系统概念英文课件:Chapter 8 Memory Management.pptVIP

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  • 2020-12-30 发布于安徽
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操作系统概念英文课件:Chapter 8 Memory Management.ppt

Operating System Concepts Address Translation Scheme Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit. Operating System Concepts Address Translation Architecture 8.* Operating System Concepts Operating System Concepts Chapter 8: Memory Management Background Swapping Contiguous Memory Allocation Paging Structure of the Page Table Segmentation Example: The Intel Pentium Operating System Concepts Objectives To provide a detailed description of various ways of organizing memory hardware(硬件组织) To discuss various memory-management techniques, including paging and segmentation(内存管理策略) To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging(段页式) Operating System Concepts Background Program must be brought (from disk) into memory and placed within a process for it to be run(程序在运行前需装入内存) Main memory and registers are only storage CPU can access directly(CPU直接访问) Register access in one CPU clock (or less)(CPU访问CPU内置寄存器) Main memory can take many cycles(CPU访问主存) Cache sits between main memory and CPU registers Protection of memory required to ensure correct operation Operating System Concepts Background Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. User programs go through several steps before being run. Operating System Concepts Base and Limit Registers A pair of base and limit registers define the logical address space Operating System Concepts Binding of Instructions and Data to Memory Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes. Address binding (地址联编,绑定) of instructions and data to memory addresses can happen at three different sta

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