EDA技术应用 7.2.4xilinx原版课件 global_time_const_8.pptVIP

EDA技术应用 7.2.4xilinx原版课件 global_time_const_8.ppt

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Global Timing Constraints Objectives After completing this module, you will be able to: Apply global timing constraints to a simple synchronous design Use the Constraints Editor to specify global timing constraints Outline Introduction Global Constraints The Constraints Editor Summary Timing Constraints and Your Project What effects do timing constraints have on your project? The implementation tools do not attempt to find the Place Route that will obtain the best speed Instead, the implementation tools try to meet your performance expectations Performance expectations are communicated with timing constraints Timing constraints improve the design performance by placing logic closer together so that shorter routing resources can be used Note: The Constraints Editor refers to the Xilinx Constraints Editor Without Timing Constraints This design had no timing constraints or pin assignments Note the logical structure of the placement and pins With Timing Constraints This is the same design with global timing constraints Note that the logic is placed closer to the I/O pins In this design, I/O flip-flops were not used Moving the logic closer to the pins improves on-chip and off-chip timing Logic Placement Can Be Very Different with Timing Constraints With global timing constraints Timing Constraints Define Your Performance Objectives Inout Pads and Synchronous Elements Make Path End Points Creating a Timing Constraint is a Two-Step Process Outline Period Constraints Cover Paths Between Synchronous Elements Period Constraints Do Not Cover Paths From Input Pads to Output Pads PERIOD Constraints Use the Most Accurate Timing Information Clock skew between the source and destination flip-flops Synchronous elements clocked on the negative edge Unequal clock duty cycles Clock input jitter An Example of the PERIOD Constraint Clock Input Jitter is One Source of Clock Uncertainty Pad to Pad Constraints Cover Purely Combinatorial Paths Offset In/Out Constrains I/O Pads To/From Syn

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