多路并行fft算法的fpga实现技术.docxVIP

多路并行FFT算法的FPGA实现技术 ： Based on the application background of radar reconnaissance receiver and the parallel operation behavior of FPGA chip ， an FFT processor structure combining the parallel processing mode with pipeline processing mode was designed to realize the digital frequency measurement of broadband. At the sampling rate of 2.4 GSPS ， the radix?2?based decimation in frequency （ DIF） algorithm is selected ， the design thought of 512?point pipeline structure FFT for each channel and 8?channel parallel processing is adopted to achieve the processing effect of 4 096?point FFT in single chan