非同步式计数器的运作.pptx

Chapter 9 Counters計數器;Figure 8--40 The J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.;Figure 9--1 A 2-bit asynchronous binary counter. ;Figure 9--3 Three-bit asynchronous binary counter and its timing diagram for one cycle. ;Figure 9--4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.;Figure 9--5 Four-bit asynchronous binary counter and its timing diagram. ;Thomas L. FloydDigital Fundamentals, 8e;Thomas L. FloydDigital Fundamentals, 8e;FigureA--21 The 74LS93A 4-bit asynchronous binary counter logic diagram. (Pin numbers are in parentheses, and all J and K inputs are internally connected HIGH.);Figure A--22 Two configurations of the 74LS93A asynchronous counter. (The qualifying label, CTR DIV n, indicates a counter with n states.);Figure A-23 74LS93A connected as a modulus-12 counter.;A 2-bit synchronous binary counter.;Figure 9--9 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal).;Figure 9--11 A 3-bit synchronous binary counter. ;Thomas L. FloydDigital Fundamentals, 8e;Figure 9--14 A synchronous BCD decade counter..;Figure A--24 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.);Figure A--25 Timing example for a 74HC163.;Figure A--26 The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.);Figure A--27 Timing example for a 74LS160.;Figure 9--16 A basic 3-bit up/down synchronous counter. ;Figure 9--17 ;Figure A--28 The 74HC190 up/down synchronous decade counter.;Thomas L. FloydDigital Fundamentals, 8e;Figure 9--18 General clocked sequential circuit.;Figure 9--19 State diagram for a 3-bit Gray code counter.;Figure 9--20 Examples of the mapping procedure for the counter sequence represented in Table 9-7 and Table 9-8.;Figure 9--21 Karnaugh maps