文本教程数电数电姜.pptxVIP

1 Chapter 7 Sequential Logic Design Principles( 时序逻辑设计原理 ) Latches and Flip-Flops (锁存器和触发器 ) Clocked Synchronous State-Machine Analysis (同步时序分析) Clocked Synchronous State-Machine Design (同步时序设计) Digital Logic Design and Application (数字逻辑设计及应用) 2 Introduction Combinational circuit Outputs depend solely on the present combination of the circuit inputs’ values Vs. sequential circuit: Has “memory” that impacts outputs too 3 Basic Concepts (基本概念) Logic Circuits are Classified into Two Types (逻辑电路分为两大类)： Combinational Logic Circuit （组合逻辑电路） Sequential Logic Circuit （时序逻辑电路） Digital Logic Design and Application (数字逻辑设计及应用) 4 Basic Concepts (基本概念) Combinational Logic Circuit （组合逻辑电路） Outputs Depend Only on its Current Inputs. (任何时刻的输出仅取决与当时的输入) Character of Circuit: No Feedback Circuit, No Memory Device (电路特点：无反馈回路、无记忆元件) Digital Logic Design and Application (数字逻辑设计及应用) 5 Basic Concepts (基本概念) Sequential Logic Circuit （时序逻辑电路） Outputs Depend Not Only on its Current Inputs, But also on the Past Sequence of Inputs. (任一时刻的输出不仅取决与当时的输入， 还取决于过去的输入序列) Character of Circuit: Have Feedback Circuit, Have Memory Device (电路特点：有反馈回路、有记忆元件) Digital Logic Design and Application (数字逻辑设计及应用) 6 Basic Concepts (基本概念) Sequential Logic Circuit （时序逻辑电路） Finite-State Machine: Have Finite States. (有限状态机：有有限个状态。） A Clock Signal is Active High if state changes occur at the clock’ Rising Edge or when the clock is High, and Active Low in the complementary case. (时钟信号高电平有效是指在时钟信号的上升沿或时钟的高电平期间发生变化。） Digital Logic Design and Application (数字逻辑设计及应用) 7 Basic Concepts (基本概念) Sequential Logic Circuit （时序逻辑电路） Clock Period: The Time between Successive transitions in the same direction. (时钟周期：两次连续同向转换之间的时间。） Clock Frequency: The Reciprocal of the Clock Period (时钟频率：时钟周期的倒数。） Digital Logic Design and Application (数字逻辑设计及应用) Figure 7-1 8 Basic Concepts (基本概念) Sequential Logic Circuit （时序逻辑电路） Clock Tick: The First Edge of Pulse in a clock period or sometimes the p