基于FPGA的数字频率计设计.doc

PAGE 基于FPGA的自适应数字频率计设计 基于FPGA的自适应数字频率计设计 Design of Adaptive Digital Frequency Meter Based on FPGA 基于FPGA的自适应数字频率计的设计 基于FPGA的自适应数字频率计的设计 基于FPGA的自适应数字频率计的设计 摘 要 本文运用EDA技术和PFGA 技术设计基于FPGA的自适应数字频率计系统。EDA技术是现代电子设计技术的核心潮流，FPGA的发展对EDA 技术起到了巨大的推动作用。运用HDL 语言，借助 EDA 开发工具，在FPGA上实现一个复杂系统的硬件电路功能具有设计灵活、高效、成本低、开发周期短的特点。 文中首先概述EDA技术，硬件描述语言VHDL, FPGA 技术及EDA 开发工具Quartus II，然后在几种常用的数字频率计的测量方法中选定直接测频法作为设计算法原理，并根据直接测频法原理建立数字频率计的系统结构框图。接下来自顶向下把数字频率计分成若干个功能模块，对每一个模块用 VHDL 语言描述并用 Quartus II 仿真，确定其功能正确实现后，再将各个模块级联起来构成数字频率计顶层电路，并对整个系统的进行仿真。最后在实验箱上对整个系统进行硬件测试。测试结果表明该数字频率计的功能得到实现，并且各项功能指标符合设计要求。 关键词：数字频率计 直接测频法 VHDL FPGA Abstract In this paper,a digital frequency meter based on FPGA is designed by using EDA technology.EDA technology is the core of modern electronic technology,The development of FPGA has played a tremendous role in promoting the development of EDA technology.By using HDL and EDA development tools, a complex hardware system on FPGA can be designed with characteristics of design flexibility, high efficiency,low cost and short development cycle. In this paper,an overview of EDA technology, hardware description language VHDL,FPGA technology and EDA development tools Quartus II is firstly given,then in several commonly used digital frequency meter measuring method,direct frequency measurement method is selected as the design algorithm.A system block diagram of the digital frequency meter is established based on the principle of direct measurement.The digital frequency meter is divided into several functional modules according to top-down method.Each module is described by VHDL and simulated by Quartus II.After determining its function correctly implemented,each module is connected together to form a digital frequency meter top-level circuit,then the whole system is simulated. Finally,the entire system is tested on the experimental development board.The test results show that the functions of digital frequency meter are realized,and the function paramete