杭电计组实验4-寄存器堆设计实验.docVIP

杭电计组实验4-寄存器堆设计实验 二、仿真波形 三、电路图 顶层电路模块 顶层电路内部结构： 四、引脚配置（约束文件） NET Clk LOC = C9; NET Reset LOC = D9; NET Write_Reg LOC = T5; NET C2 LOC = C4; # PlanAhead Generated physical constraints NET LED[7] LOC = T11; NET LED[6] LOC = R11; NET LED[4] LOC = M11; NET LED[3] LOC = V15; NET LED[1] LOC = V16; NET LED[0] LOC = U16; NET LED[2] LOC = U15; NET LED[5] LOC = N11; NET Addr[0] LOC = T10; NET Addr[2] LOC = V9; NET Addr[3] LOC = M8; NET Addr[4] LOC = N8; NET C1[0] LOC = U8; NET C1[1] LOC = V8; NET Addr[1] LOC = T9; 五、思考与探索 (1)实验四实验结果记录表 寄存器地址 写入数据 读出数据 $1 32h0000_0003 32h0000_0003 $2 32h0000_0607 32h0000_0607 $3 32hFFFF_FFFF 32hFFFF_FFFF $4 32h1111_1234 32h1111_1234 $5 32h0000_0003 32h0000_0003 $6 32h0000_0607 32h0000_0607 $7 32hFFFF_FFFF 32hFFFF_FFFF $8 32h1111_1234 32h1111_1234