ch5处理器架构计算机组织原理大连理工软件学院.pdfVIP

Computer Organization Pr iples School of Software, Dalian University of Technology Chi Lin ( Chapter Five: Processor Architecture  Processor Organization (Architecture)  Processor Implementations (Realizations)  Instruction Pipeline (Optimizations) SEQ  Drawback:  Low Through  Waste of  Big La How to enhance the efficiency ? 3 Instruction Pipeline  Computational Pipeline  Pipeline Hazards 4 Computational Logic  Delay = Combinational logic delay + register delay  A signal controls the execution of the instruction.  A non-overlap pipelined version is shown in Figure 4.32(b) 5 Pipeline  A key feature of pipelining is that it reases the throughput of the system, that is, the number of customers served per unit time, but it may also slightly rease the latency, that is, the time required to service an individual customer. 6 Di ne instruction into three stage execution model  The computation is divided into three stages, with the pipeline register latency 20ps 7 Discuss  Advantages of pipeline  Disadvantages of pipeline