超大规模集成电路第六次作业2016秋-段成华.docxVIP

The following figure shows a C2MOS based dual-edge triggered register. Its advantage is that a lower frequency clock (half of the original rate) is distributed for the same functional throughput, resulting in power savings in the clock distribution network. Calculate the timing parameters of setup time tSU, hold time tH and propagation delay tCO of the register with respect to the rising edge of the clock CLK, given that the inverter delay is tINV. Assume that the transistors are with the minimum size and C = 20 fF. Verify the function of the dual-edge triggered register and its timing param