VHDL双语教学第2章.pptVIP

VHDLSimulationSynthesis(DesignFlow/LanguageFramework)

AgendaDesignExampleBasicLanguageFramework

MajorityVoterCircuitOutput‘1’ofthereismore‘1’sthan‘0’sOutput‘0’ofthereismore‘0’sthan‘1’s多数表决器

SchematicCPLD

VHDLinQuartus

SynthesisFit

Simulation

AgendaDesignExampleBasicLanguageFramework

XYZClockDiagramXYZ(Entity)ABCFXYZ_arch1(Architecture)

XYZ.VHD(2)dataflowlibraryieee;useieee.std_logic_1164.all;---------------------------------entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXY