采样系统与时钟相位噪声和抖动的效果-AN-756.pdfVIP

AN-756 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • Tel: 781/329-4700 • Fax: 781/326-8703 • Sampled Systems and the Effects of Clock Phase Noise and Jitter by Brad Brannon ABSTRACT and supporting components have also changed and As higher resolution data converters capable of direct the focus has shifted from time domain characteristics IF-sampling come to market, system designers need help to frequency characteristics. In past times, the encode making performance/cost trade-off decisions on low jit- clock was just that—a clock. For IF and RF sampling ter clock circuits. Many of the traditional methods used to systems, the encode source is now considered more specify clock jitter are not applicable to data converters of a local oscillator than a clock for reasons discussed in or at best reveal only a fraction of the story. Without a this application note. As such, many designers expect proper understanding of how to specify and design the clock requirements to be specified in the frequency clocking circuit, optimal performance of these new data domain, just as they are for RF synthesizers. converters may not be achieved. A simple jitter specifi- While it is difficult to provide for direct correlation cation is rarely sufficient for making an informed clock between clock jitter and phase noise, this application selection. Rather, it