基于FPGA的可编程高速路由查找算法研究与实现.doc

摘要 随着 IP 网络的高速发展，各种多媒体业务也应运而生，人们对网络的速度要求也越来 越高。路由查找速度成为了制约网络速度的瓶颈。一般的软件查找算法难以达到速度要求， 因此对硬件查找算法的研究显得尤为重要。 论文首先概述了课题背景及研究内容，介绍了一些已有的算法，包括若干典型的硬件算 法，总结了各个算法的优缺点。接着，论文提出了一种 FPGA 硬件平台上基于二叉树的最长前 缀匹配路由查找算法及其实现结构 BstLpmF(Binary Search Tree-Based Longest Prefix Match for Fpga)，利用硬件的并行处理和流水线设计，大幅度提高了查找速度与效率，并引 入低功耗设计思想，降低了整个算法结构的功耗。论文还设计了完善的路由转发表更新消息， 使得 FPGA 中的路由转发表的更新方便简单，且不影响正常的查找操作。然后论文详细介绍了 该算法在 FPGA 中的设计实现，在 Xilinx ISE 10.1 软件中完成了各个模块的编码，在 Synplify Pro 9.6.2 软件中完成了综合。最后利用 Modelsim 软件对算法实现进行了功能仿真，设计了 完备的仿真案例，仿真结果表明所提出的设计功能正确，具有很高的查找速率，可以达到 374MLPS（Millions Lookups per Second），完全满足设计要求。 关键词: 硬件路由查找，FPGA ，并行处理 ，流水线设计 I Abstract With the development of high-speed IP networks, multimedia services have emerged. The requirement on network speed is increasingly stringent, in which lookup speed of network routers  has become a bottleneck. Considering that software-based routing search  is difficult to achieve the  high speed required, hardware-based search technique is of special importance. Following an outline of the technical background and research contents, the dissertation introduces the existing lookup algorithms, including some typical hardware-based algorithms  Together with a summary of the pros and cons of each algorithm. Then,  a routing lookup  hardware structure BstLpmF (Binary Search Tree-Based Longest Prefix Match for Embedded - Fpga) is proposed based on FPGA platform. The use of parallel processing and pipeline hardware  design  greatly improves the search speed and efficiency.  Low power design approach is  employed to reduce the power consumption of the entire structure. A high performance routing update message is designed to make the FPGA routing table simple and easy to update with no adverse impact on the normal operation of lookup. Furthermore the design and implementation of the FPGA structure is detailed, including individual module coding using Xilinx ISE 10.1 software and system synthesis using Synplify Pro 9.6.2 software. Finally functio