中科院_数字集成系统设计_作业1.docVIP

数字集成系统设计作业 Assignment 1: Question 1: ITRS: International Technology Roadmap for Semiconductors. Gate-Equivalent: A gate equivalent stands for a unit of measure which allows specifying manufacturing-technology-independent complexity of digital electronic circuits. Technology Nodes: A technology node is defined as the ground rules of a process governed by the smallest feature printed in a repetitive array. Feature size: The size of the elements on a chip, which is designated by the DRAM half pitch. The smallest feature size is generally smaller than the feature size for a technology generation. Behavioral representation: It represents a design as a black box and describes its outputs in term of the input and time. Structural representation: In structural representation, a black box is represented as a set of components and connections. It may be generated by mapping functioned representation onto a set of components and connections. Geometrical representation: It ignores what the design is supposed to do and binds its structure in space or to silicon. It entails the specification of all geometric patterns defining the physical layout of the chip, as well as their position. Abstraction hierarchy: Abstraction hierarchy is a human invention designed to assist people in engineering very complex systems by ignoring unnecessary details. Refinement: Refinement is a process of purification, which is used when behavioral representation transfers to geometrical representation. System-level synthesis: It deals with the transformation of an abstract model of behavior into a model consisting of standard functional units. Logic synthesis: Logic-level synthesis deals with the transformation of a macroscopic model to an interconnection of logic primitives. These primitives determine the microscopic structure of the circuits. Layout synthesis: It consists of creating a physical view at the geometric level. It entails the specification of all geometric patterns defining the physical l