6-2译码器chenyu.pptVIP

Class exerciserealize the logic function F with 3-to-8 decoder and logic gates. 6.4 decoder 译码器 Review of Last Class 6.4.1Binary Decoder (二进制译码器) n-to- 2n decoder The most common decoder circuit is an n-to-2n decoder or binary decoder. Such a decoder has an n-bit binary input code and a 1-out-of-2n output code. Review of Last Class n-to- 2n decoder 6.4.2 Logic Symbols for Larger-Scale Elements Review of Last Class The 74x138 is a commercially available MSI 3-to-8 decoder. the 74x138 has active-low outputs. 补充：用译码器和逻辑门实现逻辑函数 用译码器和逻辑门实现逻辑函数 用译码器和逻辑门实现逻辑函数 How to design the 4-to-16 decoder? 6.4.4 Cascading Binary Decoders (级联二进制译码器）(P390) Example 5:design the 5-to-32 decoder 补充：用译码器和逻辑门实现逻辑函数 用译码器和逻辑门实现逻辑函数 用译码器和逻辑门实现逻辑函数 BCD Decoder (二－十进制译码器) 6.4.8 Seven-Segment Decoders (七段显示译码器) (P408) Seven-Segment Decoders(七段显示译码器) Input code: 4-bit BCD [ 输入信号：BCD码（用A3A2A1A0表示）] Output Code: Seven-Segment Code [ 输出：七段码（的驱动信号）a ~ g ] 1 表示亮(On)，0 表示灭(Off) Decoders in Verilog Chapter 6 Table 6-20 . the decoder in Figure 6-32 module vr2to4dec(I0,I1,EN,Y0,Y1,Y2,Y3); input I0,I1,EN; output Y0,Y1,Y2,Y3; wire NOTI0,NOTI1; INV U1(NOTI0,I0); INV U2(NOTI1,I1); AND3 U3(Y0,NOTI0,NOTI1,EN); AND3 U4(Y1, I0, NOTI1,EN); AND3 U5(Y2,NOTI0, I1, EN); AND3 U6(Y3, I0, I1, EN); endmodule case语句 c a s e(c a s e _ e x p r) c a s e _ i t e m _ e x p r{ ,c a s e _ i t e m _ e x p r} :p r o c e d u r a l _ s t a t e m e n t . . . . . . [d e f a u l t: p r o c e d u r a l _ s t a t e m e n t] e n d c a s e c a s e语句首先对条件表达式c a s e _ e x p r求值，然后依次对各分支项求值并进行比较，第一个与条件表达式值相匹配的分支中的语句被执行。可以在1个分支中定义多个分支项；这些值不需要互斥。缺省分支覆盖所有没有被分支表达式覆盖的其他分支。 分支表达式和各分支项表达式不必都是常量表达式。 Table 6-21. 3-to-8 binary decoder module vr74x138a(G1,G2A_L,G2B_L,A,Y_L); input G1,G2A_L,G2B_L; input [2:0] A; output [0:7] Y_L; reg [0:7] Y_L; always @(G1 or G2A_L or G2B_L or A) begin