【13加电容】【窄带】Design and Performance Analysis of a 866-MHz.PDFVIP

1840 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 60, NO. 5, MAY 2013 Design and Performance Analysis of a 866-MHz Low-Power Optimized CMOS LNA for UHF RFID Jack Li and S. M. Rezaul Hasan, Senior Member, IEEE Abstract—An optimized 866 MHz CMOS LNA for UHF radio- 866 MHz, transforms such RFID LNA design optimization frequency identification reader is presented. It achieves simulta- into a challenging task. Various techniques for narrow-band neous impedance and minimum Fmin noise matching at a very LNA optimization with respect to power dissipation, noise, low-power drain of 850 μW from a 0.7-V supply voltage. Com- pared to other GHz LNA designs, this UHF LNA design using and impedance matching have been reported, such as, classical sub-1 V supply voltage is quite challenging due to the inductor noise matching [10], simultaneous noise and impedance match- size and bias drain-related noise factor degradation. The LNA was ing (SNIM) [11], power-constrained noise optimization [12], fabricated using the 130-nm IBM CMOS process. Compared to and power-constrained simultaneous noise and input matching previously reported narrow-band LNA designs, inclusion of the (PCSNIM) [15]. The above approaches lacked mutual con- finite gds effect is found to improve the nanometric design opti- mization. The low-cost packaged LNA was tested using external sistency. Hence, the authors in [16], [17], provided an inte- lumped element and microstrip line matching. The LNA delivered grated analysis of the above narrow-band LNA optimization a power gain (S21 ) of ≈17 dB and an input power reflection (S11 techniques based on a consistent