计算机结构组成课件.pptVIP

CS61C L221 Performance ? UC Regents How to Design a Processor: step-by-step 1. Analyze instruction set architecture (ISA) = datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Clocking Methodology Storage elements clocked by same edge Being physical devices, flip-flops (FF) and combinational logic have some delays Gates: delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF (set-up time), and we have the usual clock-to-Q delay “Critical path” (longest path through logic) determines length of clock period Register-Register Timing: One complete cycle 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] 3c: Logical Operations with Immediate R[rt] = R[rs] op ZeroExt[imm16] ] 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 3d: Load Operations R[rt] = Mem[R[rs] + SignExt[imm16]] Example: lw rt,rs,imm16 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 3e: Store Operations Mem[ R[rs] + SignExt[imm16] ] = R[rt] Ex.: sw rt, rs, imm16 3f: The Branch Instruction beq rs, rt, imm16 mem[PC] Fetch the instruction from memory Equal = R[rs] == R[rt] Calculate branch condition if (Equal) Calculate the next instruction’s address PC = PC + 4 + ( SignExt(imm16) x 4 ) else PC = PC + 4 Datapath for Branch Operations beq rs, rt, imm16 Datapath generates condition (equal) Putting it All Together:A Single Cycle Datapath An Abstract View of the Implementation An Abstract View of the Critical Path Administrivia Frid