SingleSequence的边界约束条件.pdfVIP

第37 卷 第1 期 电 子 科 技 大 学 学 报 Vol.37 No.1 2008 年1 月 Journal of University of Electronic Science and Technology of China Jan. 2008 Single-Sequence的边界约束条件 1,2 1 1 李 康 ，虞厥邦，于永斌 (1. 电子科技大学电子工程学院 成都 610054; 2. 四川交通职业技术学院 成都 611130) 【摘要】在VLSI物理设计中，分层设计和连线优化都要求某些模块放置在布局的边界位置。该文针对一般的具有不可二 划分结构的布图规划问题，在SS编码的基础上解决VLSI物理设计中有边界约束的布局布图规划的问题；证明SS的放置顺序是 表示模块的数字在SS 中出现的位置先后顺序；提出模块放置在四个边界(上、下、左、右边界)在SS编码中应满足的充要条件 及证明；并给出模块位于四个边界在SS编码中相应的表达式和计算方法。 关 键 词 边界约束; 布图规划; 布局; VLSI物理设计 中图分类号 TP391.7 文献标识码 A Boundary Constraints Using Single-Sequence Representation 1,2 1 1 LI Kang ，YU Jue-bang ，YU Yong-bin (1. School of Electric Engineering, University of Electronic Science and Technology of China Chengdu 610054; 2. Sichuan Vocational and Technical College of Communication Chengdu 611130) Abstract In practice of floorplan/placement of very large scale integration (VLSI) physical design, it is very critical to place some modules along the boundaries of the chip so that connections between inputs and outputs and among units in hierarchical design mode are shortened. Based on non-slicing representation single-sequence (SS), boundary constraints in VLSI layout design are solved. The packing sequence of a SS is proved to be the appearance sequence of integer, which represents module in a SS code. Further, a necessary and sufficient condition of a module to be placed on four boundaries (top, bottom, left, and right) in a SS code is proposed and proved. Key words boundary constraint; floorplan; placement; VLSI physical design 随着电子技术的发展，电路的规模与设计复杂 置问题有十分重要的理论和现实意义。 度迅