ECE 448Lecture 13.ppt

Sources Simple Testbench Advanced Testbench Assert Assert is a non-synthesizable statement whose purpose is to write out messages on the screen when problems are found during simulation. Depending on the severity of the problem, The simulator is instructed to continue simulation or halt. Assert - syntax ASSERT condition [REPORT message [SEVERITY severity_level ]; The message is written when the condition is FALSE. Severity_level can be: Note, Warning, Error (default), or Failure. Assert - Examples assert initial_value = max_value report initial value too large severity error; assert packet_length /= 0 report empty network packet received severity warning; assert false report Initialization complete severity ?note”; Report - syntax REPORT message [SEVERITY severity_level ]; The message is always written. Severity_level can be: Note (default), Warning, Error, or Failure. Report - Examples report Initialization complete; report Current time = timeimage(now); report Incorrect branch severity error; Report - Examples library IEEE; use IEEE.STD_LOGIC_1164.all; entity example_1_tb is end example_1_tb; architecture behavioral of example_1_tb is signal clk : std_logic := 0; begin clk = not clk after 100 ns; process begin wait for 1000 ns; report Initialization complete; report Current time = timeimage(now); wait for 1000 ns; report SIMULATION COMPLETED severity failure; end process; end behavioral; Records type opcodes is (add, sub, and, or); type reg_number is range 0 to 8; type instruction is record opcode : opcodes; source_reg1 : reg_number; source_reg2 : reg_number; dest_reg : reg_number; end record instruction; constant add_instr_1_3 : instruction:= (opcode = add, source_reg1 | dest_reg = 1, source_reg2 = 3); Variable – Example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Numbits IS PORT ( X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; Coun