Impedance.pptVIP

P*/P29 阻抗控制設計與運用 T A POWER/GROUND SIGNAL W SIGNAL W T A A D POWER/GROUND POWER/GROUND 在磁場區裡之條線(STRIPLINE ) 磁場 靜電場 *注意: 當電流流動時其磁場就產生. 當有電壓時其靜電場就產生. *注意: 當電流流動時其磁場就產生. 當有電壓時其靜電場就產生. Noise Source in an Ecl. Based System (34%) (5%) (16%) (5%) (16%) (7%) (8%) (9%) Total of All Noise Sources = 224 mV Available Noise Budget = 125 mV Excess Noise = 99 mV Impedance Mismatch Sources ? Changes in trace width ? Stubs ? Loads ? Connector transitions ? Poorly matched terminations or lack of terminations ? Large power plane discontinuities ? In other words, anything that can change the Lo or Co of a transmission line will change its impedance. NOTE: In spite of popular held beliefs, vias and right angle bends are not measure sources of impedance mismatch. 阻抗控制需求決定條件 ? 工作頻率(影響rise time) ? 傳輸線之長度 ( 造成propagation delay ) ? 所以工作頻率越高,傳輸線過長需考慮作阻 抗控制. ? ? ? ? 所以工作頻率越高,傳輸線過長需考慮作阻 抗控制. When is Reflection Important? ? Reflections can usually be ignored when the rise time of a signal is slow relative to propagation delay ? Rule of thumb - When the rise time is shorter than about 8 times the propagation delay ,transmission line effects become significant. That is , if Rise Time Propagation Delay ≦ 8 Rise Time and Propagation Delay Examples #1 - 10 Ns rise time (typical TTL) - 1 Ns interconnect delay (~ 6 inches) 10 ns 1 ns No Problem Rise Time and Propagation Delay Examples #2 - 0.5 Ns rise time (ECL or advanced CMOS Logic) - 1 Ns interconnect delay (~ 6 inches) Reflection occur at any rise time , however, at slower rise times they not be significant in the circuit 0.5 ns 1 ns Reflection 傳輸線構成之三要素 訊號線 介質層 接地層 + + 傳輸線 傳輸線構成之三要素 傳輸線構成之三要素 阻抗匹配之三個要素 輸出阻抗 (原始主動零件) 特性阻抗 (訊號線) 輸入阻抗 (被動零件) 阻抗匹配 (Impedance Match) 阻抗匹配之三個要素 阻抗匹配之三個要素 阻抗控制設計流程圖 (Impedance Control Design Flow Chart) 資料接收 ( Data come-in) 阻抗控制設計 ( Impedance Control) 製作規範填寫 ( Run-Card Issue) 底片設