基于FPGA出租车计价器设计详解.docVIP

题目：基于FPGA出租车计价器设计 基于FPGA出租车计价器的设计 摘　　要 本文介绍了一种采用进行出租车计器的设计作为专用集成电路（ASIC）领域中的一种半定制电路而出现的，既解决了定制电路的不足，又克服了原有可编程器件门电路数有限的缺点。本设计实现了出租车计器所需的一些基本功能Quartus II9.0软件平台下，采用Verilog HDL 硬件描述语言分别设计了分频模块、计程模块计费模块译码动态扫描模块出租车计器五大模块对每个模块和主程序分别进行了仿真，并对仿真波形作了分析计程模块计费模块译码动态扫描模块Quartus II；Verilog HDL Based on the FPGA Design of Taxi Meter ABSTRACT This article describes the design ideas and methods of the taximeter, through the programmable logic device (FPGA/CPLD). Using programmable logic devices design on the other hand, peripheral circuit is simple, convenient modular design, the principle is clear, fast, strong function, high reliability, strong flexibility, and complete and additional functional extension. This design has realized the taxi meter required some basic functions, such as log, timing, pricing, dynamic display, billing amount fare and mileage charging, waiting for the timing. Through the Quartus II 9.0 Software Platform，using Verilog HDL language completed the description and simulation of frequency module, the meter module, Billing module, timing modules, decoding, dynamic scanning display module,for each module are simulated respectively and top-level module with schematic design , the simulation waveform were analyzed. After download validation hardware, completed the taxi meter divider module, log module, billing module, timing module, decoding and dynamic scanning display modules designed to achieve. Keywords: FPGA；Taximeter；Quartus II；Verilog HDL 目　　录 1　前言 1 1.1　课题的来源及意义 1 1.2　国内外发展状况 1 1.3　研究的手段及目标 2 2　总体方案设计 3 2.1　方案论证与选择 3 2.2　设计思想及原理 4 3　FPGA、Verilog及QuartusⅡ开发环境的介绍 6 3.1　现场可编程门阵列FPGA 6 3.2　硬件描述语言Verilog HDL 6 3.3　QuartusⅡ开发环境 7 4　设计与仿真验证 8 4.1　分频模块 8 4.1.1　计程分频模块 8 4.1.2　计时分频模块和计费分频模块 9 4.1.3　数码管动态显示模块 9 4.1.4　数码管动态显示模块仿真 9 4.2　计程模块 10 4.2.1　计程模块电路 10 4.2.2　计程模块仿真 11 4.3　计时模块 12 4.3.1　计时模块电路 12 4.3.2　计时模块仿真 13 4.4　计费模块 13 4.4.1　计费模块电路 13 4.4.2　计费模块仿真 14 4.5　数码管显示模块 16 4.5.1　数码管显示模块电路 16 4.5.2　数码管显示仿真 16 4.6　整体顶层模块设计电路 17 4.7　下载实现 19 5　结论 22 参考文献 23