基于NiosII的数字钟设计剖析.doc

基于Nios II的数字钟设计 学生姓名： 学生学号： 院（系）： 电气信息工程学院 年级专业： 电子信息工程 指导教师： 助理指导教师： 二〇一五年五月  摘 要 传统的设计技术已经不足以满足系统化、网络化、高速度、低功耗、多媒体等实际需要。SOPC用可编程技术把整个系统放在单一的一个芯片上，因此具有灵活、高效、设计可重用等特性。在SOPC系统中，本来需要上几千行的HDL代码的复杂功能模块，经过嵌入IP核后，只需要几十行的C代码就可以简单的实现，由此可以让整个设计规模、功能、功耗、性能指标、开发成本等多个方面实现优化。本论文主要介绍基于NIOS II 的SOPC设计一个数字钟的方法和流程。在本设计中主要分为硬件设计部分和软件设计部分。本系统的硬件开发是根据我所用的FPGA黑金开发板实际器件搭建的，采用QuartersⅡ作为仿真平台。主芯片采用的是Altera 公司的cyclone VI 系列的EP4CE15F17C8N芯片，本设计的软件是用C语言写的，系统是一个数字时钟，因为本设计是通过6个数码管来显示时间的，所以只能显示小时、分钟和秒，满刻度时显示23时59分59秒。在每个设计部分中，都给出了详细的设计方法。通过本次设计可以了解SOPC的开发设计流程，体现FPGA在电子设计领域的广泛应用。 关键词 数字钟，SOPC，Nios II，FPGA  ABSTRACT The traditional design techniques have been insufficient to meet the actual needs systematic, network-based, high-speed, low-power, multimedia. SOPC programmable technology to the entire system on a single chip, it has a flexible, efficient design reuse and other features. In SOPC system, would have required the HDL code thousands of lines of complex modules, after embedded IP core, only a few dozen lines of C code can be simple to achieve, which can make the entire design size, function, power aspects of consumption, performance, optimize development costs. This paper describes the methods and processes based on the NIOS II SOPC design a digital clock. In this design it is divided into hardware design and software design. Hardware development of this system is based on an actual device FPGA development board black gold I used to build, using QuartersⅡ as the simulation platform. The main chip is Alteras cyclone VI series EP4CE15F17C8N chip, the design of the software is written in C language, the system is a digital clock, because of the design of digital control by 6 to display the time, we can only display hours, minutes and seconds display 23:59:59 full scale. In each design section, we are given detailed design. Through this design can understand SOPC development and design process, reflect FP