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ibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_Unsigned.all; use ieee.std_logic_ARITH.all; entity DingCeng is port( a:in std_logic_vector(2 downto 0); clk:in std_logic; hang:out std_logic_vector(7 downto 0); lie:out std_logic_vector(7 downto 0)); end entity DingCeng; architecture one of DingCeng is component zhou is port(clk,en:in std_logic; lie:out std_logic_vector(7 downto 0); com:out std_logic_vector(7 downto 0)); end component; component shu is Port( clk,en:in std_logic; lie:out std_logic_vector(7 downto 0); com:out std_logic_vector(7 downto 0)); end component; component Hao is PORT( clk,en:IN STD_LOGIC; lie:out STD_LOGIC_VECTOR(7 DOWNTO 0); com:out STD_LOGIC_VECTOR(7 DOWNTO 0)); end component; signal h1,h2,h3:std_logic_vector(7 downto 0); signal l1,l2,l3:std_logic_vector(7 downto 0); begin u1:zhou port map(clk=clk,en=a(2),com=h1,lie=l1); u2:shu port map(clk=clk,en=a(1),com=h2,lie=l2); u3:Hao port map(clk=clk,en=a(0),com=h3,lie=l3); process(a) begin if a(2)=0 and a(1)=1 and a(0)=1 then hang=h1;lie=l1; elsif a(1)=0 and a(2)=1 and a(0)=1 then hang=h2;lie=l2; elsif a(0)=0 and a(2)=1 and a(1)=1 then hang=h3;lie=l3; else hanglie end if; end process; end architecture one; Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Use ieee.std_logic_arith.all; entity Hao is port( clk,en:IN STD_LOGIC; lie:out STD_LOGIC_VECTOR(7 DOWNTO 0); com:out STD_LOGIC_VECTOR(7 DOWNTO 0)); end Hao; Architecture a OF Hao IS signal st1:std_logic_vector(7 downto 0); signal osc:std_logic; signal osd:std_logic; signal d_ff:std_logic_vector(27 downto 0); signal data:std_logic_vector(7 downto 0); signal d0,d1,d2,d3,d4,d5,d6,d7:std_logic_vector(7 downto 0); signal lie0:std_logic_vector(6 downto 0); Begin Com=data; lie=st1;