Design and Performance of the 6 GSs .pptVIP

Oct. 21st, 2008 IEEE/NSS Dresden Design and Performance of the 6 GS/s Waveform Digitizing Chip DRS4 Stefan Ritt Paul Scherrer Institute, Switzerland Switched Capacitor Array Cons No continuous acquisition No precise timing External commercial ADC needed Pros High speed 6 GHz high resolution 11.5 bit resol. High channel density 9 channels on 5x5 mm2 Low power 10-40 mW / channel Low cost ~ 10$ / channel DRS4 Fabricated in 0.25 mm 1P5M MMC process UMC , 5 x 5 mm2, radiation hard 8+1 ch. each 1024 cells Differential inputs,differential outputs Sampling speed 500 MHz … 6 GHz,PLL stabilized Readout speed 30 MHz, multiplexedor in parallel ROI readout mode Daisy-chaining of channels Daisy-chaining of channels Single Channel Chip Daisy Chaining Simultaneous Write/Read Trigger an DAQ on same board Using a multiplexer in DRS3, input signals can simultaneously digitized at 65 MHz and sampled in the DRS FPGA can make local trigger or global one and stop DRSupon a trigger DRS readout 6 GHz samples though same 8-channel FADCs DRS4 Test Results On-chip PLL Bandwidth Bandwidth is determined by bond wire and internalbus resistance/capacitance: 850 MHz QFP , 950 MHz QFN , flip-chip Timing jitter Fixed jitter calibration Fixed Pattern Jitter Results Random Jitter Results Experiments using DRS chip Availability DRS4 will become available in larger quantities in November 2008 Chip can be obtained from PSI on a “non-profit” basis Delivery “as-is” Reference design schematics from PSI Costs ~ 10-15$/channel VME boards from industry in 2009 Conclusions Fast waveform digitizing with SCA chips will have a big impact on experiments in the next future DRS4 chip solves all known issues of DRS3 and adds more flexibility DRS4 has 6 GHz, 1024 sampling cells per channel, 9 channels per chip, 11.5 bit vertical resolution, 3 ps timing resolution ~4000 DRS channels already used in several experiments, hope that other experiments can benefit from this technology A