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Development and Application of Tree Synthesis Algorithms
Development and Application of Tree Synthesis Algorithms Overview Part I: Buffer tree synthesis Formulations S/P/SP-tree Part II: Fanin tree embedding/replication Optimization across gate boundaries Interaction with placement Part I: Buffer Tree Synthesis Premises of Work MAIN PREMISE: Powerful Buffer Tree Synthesis is a Core for Modern Design Max Slack Weakness Problem Formulation Given: Location of Driver and Sinks Technology Parameters Timing Requirements Buffer Library Target Routing Graph (Blockages) Find: Topology in corresponding space its Embedding and Buffer Assignment Minimizing Cost s.t. Timing Constraints Philosophy of Constraint Imposition Goals: Predictable Behavior Absence of ad-hoc Heuristics Main Idea: Optimally Solve Constrained Variant of the Problem Well-Designed Constraints Produce Large Flexible Solution Space Tractability Constraints: Topology Space Topology Embedding Flexibility Target Routing Graph Construction Algorithmic Description Timing-Driven Maze Routing Topology Embedding S-Tree P-Tree SP-Tree Algorithmic Description Timing-Driven Maze Routing Topology Embedding S-Tree P-Tree SP-Tree Core Subroutine: Timing-Driven Maze Routing Generalization of [Hur, et. al.; TCAD Feb 2000] Single Target, Multiple Sources Finds non-dominated paths Simultaneous Buffer Insertion Handling of Blockages in Topology Synthesis Algorithmic Description Timing-Driven Maze Routing Topology Embedding S-Tree P-Tree SP-Tree Topology Embedding Goal: Obtain timing feasible embedding / buffering of given topology, minimizing cost Solution: Dynamic Programming (bottom-up) Solution sets A(u,v) represents a set of solutions that correspond to Vertex u in Topology Vertex v in Target Graph A1b = Join(A1.left , A1.right) A1 = GenDijsktra(A1b) Recurrence Relation A1 - candidate solutions for subtree rooted at u in T, with u placed at v in G A1b - candidate solutions for subtree roote
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