视频信号处理多媒系统工程师.docVIP

Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications??Original Research ArticleJournal of Visual Communication and Image Representation This paper presents a novel hardware implementation of a disparity estimation scheme targeted to real-time Integral Photography (IP) image and video sequence compression. The software developed for IP image compression achieves high quality ratios over classic methodologies by exploiting the inherent redundancy that is present in IP images. However, there are certain time constraints to the software approach that must be confronted in order to address real-time applications. Our main effort is to achieve real-time performance by implementing in hardware the most time-consuming parts of the compression algorithm. The proposed novel digital architecture features minimized memory read operations and extensive simultaneous processing, while taking into concern the memory and data bandwidth limitations of a single FPGA implementation. Our results demonstrate that the implemented hardware system can successfully process high resolution IP video sequences in real-time, addressing a vast range of applications, from mobile systems to demanding desktop displays. Article Outline 1. Introduction 2. Algorithm description 2.1. Motion estimation 2.2. Compression method 3. Hardware design 3.1. System overview 3.2. Datapath 4. Results 5. Discussion—Future work Acknowledgements References A dedicated media processor is used in many mobile consumer devices to accelerate video, image, graphics, and display processing. Increased demand for higher pixel resolution, higher quality image and video processing, more graphics performance necessitates dramatically increased signal processing capabilities. To provide the increased performance at acceptable cost and power requires redesign of the traditional architecture. By wisely partitioning algorithms across programmable and fixed-function