Topic_04_behavioral_Synthesis_08.ppt

Semantics: Sequential Concurrent Statements There are two types of statements Sequential Statements within a process Evaluated sequentially during simulation and UPDATED AT the END of PROCESS Concurrent Statements outside of a process Processes are evaluated concurrently Signal Assignments Signal assignment is the basic form of behavioural modelling in VHDL and takes the following basic form signal-object = expression after delay-value; PAR= PAR1 xor DIN after 12 ns; when a signal assignment statement is executed , the value of the expression is computed , and this value is scheduled to be assigned to the signal after the specified delay( known as the inertial delay). The delay value is ignored in Synthesis If a signal assignment is made in the architecture it will be regarded as a concurrent statement. VHDL Design Styles Processes in VHDL Processes Describe Sequential Behavior Processes in VHDL Are Very Powerful Statements Allow to define an arbitrary behaviour that may be difficult to represent by a real circuit Not every process can be synthesized Use Processes with Caution in the Code to be Synthesized Use Processes Freely in Testbenches Anatomy of a Process The Process Sensitivity List A Process is invoked when one or more of the signals within the sensitivity list change, e.g. ARCHITECTURE archlist OF list IS BEGIN nand: PROCESS (a,b) BEGIN c = NOT (a AND b); END PROCESS nand; END archlist; PROCESS with a SENSITIVITY LIST List of signals to which the process is sensitive. Whenever there is an event on any of the signals in the sensitivity list, the process is triggered. Every time the process is triggered, it will run in its entirety. WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST. label: process (sensitivity list) declaration part begin statement part end process; Process statements/Wait statement The process statements can be suspended by means of a wait statement. There are three basic forms for the wa