Intel微机原理第2章(微处理器及其结构)-1.pptVIP

利用段选择子确定段基地址和段界限 ?DS=0020H=0000000000100000B，则INDEX=4，TI=0 表示选择第4个描述符（INDEX=0，TI=0时，有特殊用途，全局描述符从1开始， 必须有DUMMY DESRIPTOR 〈 〉） 段起始地址为561234H，段界限为5678H ?????? 保护工作方式下的地址形成机制 选择子 偏移量 : 段机制 页机制 15 0 31 0 线性地址 PG=0 物理地址 32 32 2-4 Memory Paging 存储器分页机制 存储器分页机制将存储器分成长度固定的页，每页4KB。 由程序产生的线性地址(linear address)通过 分页机制转换成存储器特定位置的物理地址(physical address), 它使物理存储器定位于任意的线性地址上。 分页单元(paging unit)由微处理器内的控制寄存器(32位)CR0-CR4控制，这些控制寄存器保存各种全局性状态信息，影响系统所有任务的运行。它们主要提供操作系统使用。 控制寄存器 Control Register  The paging system operates in both real and protected mode. It is enabled by setting the PG bit to 1 (left most bit in CR0).(If set to 0, linear addresses are physical addresses). CR3 contains the page directory “physical” base address. The value in this register is one of the few “physical” addresses you will ever refer to in a running system. The page directory can reside at any 4K boundary since the low order 12 bits of the address are set to zero. The page directory contains 1024 directory entries of 4 bytes each. Each page directory entry addresses a page table that contains up to 1024 entries. 线性地址 Linear Addresss 线性地址到物理地址的转换 转换检测缓冲器 TLB The current scheme requires three accesses to memory: One to the directory, one to the appropriate page table and (finally) one to the desired data or code item. A Translation Look-aside Buffer (TLB) is used to cache page directory and page table entries to reduce the number of memory references . Plus the data cache is used to hold recently accessed memory blocks(80486 holds 32 most recent page translation addresses and Pentium and above contain separate TLBs for each of their instruction and data caches. P.69~70 1,4,11,13,15,17,24,25,27,28,29,31,35,38,40,41,42,44 苏州大学计算机科学与技术学院 第*页 微型计算机技术课程讲义 第二章 微处理器及其结构 2-1 编程结构 2-2 实模式存储器寻址 2-3 保护模式存储器寻址 2-4 存储器分页机制 2-1 编程结构(8086) 总线接口部件BIU (Bus Interface Unit) 执行部件EU (Execution Unit) 总线接口部件BIU