performance-drivenlayoutmethodology-研究领域-HDL-Based.ppt

HDL-Based Layout Synthesis Methodologies Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {Email: chunghaw@cs.nthu.edu.tw} Outline Introduction Timing analysis Design planning RTL timing budgeting A timing-driven soft-macro placement and resynthesis method Discussion Why Needs HDL-based Design Methodologies? An HDL-based Design Flow Top-Down Design Methodology Applications and Layout Architectures Layout-driven Design methodology Design Estimation Timing Area Power Statistic VS. quick-synthesis methods Analytical VS. constructive methods Outline Introduction =Timing analysis Design planning RTL timing budgeting A timing-driven soft-macro placement and resynthesis method Summary Minimum Cycle Time Timing Analysis Critical path delay analysis Clock skew analysis Timing analysis at different design levels Delay calculation Parasitic extraction Accuracy VS. fidelity Timing Analysis RTL and Logic-level Timing Analysis RTL Timing Analysis Chip-level Timing Analysis Macro-level Timing Analysis Accuracy of Timing Analysis Outline Introduction Timing analysis = Design planning RTL timing budgeting A timing-driven soft-macro placement and resynthesis method Summary Design Planning Macro definitions Soft macro generation Macro placement Pin assignment Chip Planning I Chip Planning II Design Planning Considerations How much timing, area, and power budgets should be assigned to each macro? How to generate soft macros? - top-down - bottom-up How to layout clock and power/ground network? Design Budgeting Soft Macro Generation Soft Macro Generation (Cont.) Design Hierarchy Preservation Clock Network Styles Mesh: robust, large area and power Trunk: simple Tree: min area, many supporting design algorithms Clock Issues at RTL RTL Timing Analysis Timing-critical Macro Detection RTL Design Planning Outli