ICLayoutdigitallayout.ppt

* * * * * * * * /users/kia/Courses/EE5301/ VLSI Design Automation I – ? Kia Bazargan * * * * * * * * * 0.55 micron CMOS, 4 layer metal Clock load accounts for 40% of the total effective capacitance of the chip EE141 * EE141 * EE141 * * * * * * * * * * * * * * * * * * * * Digital Layout * Central Clock Trunk driver Clock Routing Trunk or Grid Multiple Clock Domains Clock Mesh * Digital Layout * 在完成电源网络和时钟网络的布线后，要考虑其他关键网络。通常根据一个说明芯片关键网络的列表来对它们进行布线。 * Digital Layout * 其他网络的布线 将关键网络的文件送入自动布线器，在完成芯片的大部分布线之前，在布线还相对比较容易的时候先对这些关键网络进行布线。同样，你可以在任何时候进行人工干预，直到所有的关键网络完全达到你的要求。 最后要做的是对电路中余下的部分进行布线。通常是由自动布线工具来完成。 * Digital Layout * 布线完成后，计算机会输出一个布线文件，给出所布线的实际布线长度和实际的导线电容。如果不需要调整，这就是最终的真实数据。 压缩Compaction –从所有方向压缩版图以使芯片总面积最小。 * Digital Layout * 版图设计流程 /4 通道压缩 Channel Compaction ( one dimension) X-compaction Y-compaction 面积压缩Area Compaction (1.5 or 2 dimension) May need a lot of constraints to get desired results * Digital Layout * * Digital Layout * 版图设计流程 /5 验证Verification – 检查版图设计的正确性。包括DRC (design rule checking )－用以确保版图设计满足工艺加工约束的设计规则检查，和 LVS－用以确保版图设计与电路设计完全匹配的版图电路一致性检查， 以及性能验证－提取几何信息来计算电阻、电容和延迟时间等以实际的布线数据来模拟以确保版图设计的性能达到要求的检查。 提取Extraction : 又称为电路提取(Circuit extraction )，即从版图中产生电路以与原始的电路网 表相比较。 Physical verification is the process of checking that the finished layout complies with the manufacturing rules associated with this process and agrees with the schematic/netlist. The former is DRC, and the latter is LVS. * Digital Layout * 物理验证 Physical Verification Physical verification, as its name suggest, focuses on the physical aspects of the design. This verification process has nothing to do with the timing or logic aspects of the design. Performance verification is the process of checking the logic and timing aspects by back-simulation with the netlist with reverse-labeled parasitic parameters after extraction. * Digital Layout * Performance Verification The logic aspects of the design are verified by simul