projectcodebs02.docVIP

Project Code: BS02  Crypto Acceleration Using Asynchronous FPGAs A Major Qualifying Project Report Submitted to the faculty of WORCESTER POLYTECHNIC INSTITUTE In partial fulfillment of the requirements for the Degree of Bachelor of Science Submitted By: _______________ _______________ Bryce Barcelo John Taylor Sponsored by: General Dynamics C4 Systems 77 A Street Needham, MA 02494 Liaisons: Brendon Chetwynd Gerardo Orlando Submitted To: _______________ Prof. Berk SunarAbstract The goal of this project, sponsored by General Dynamics C4 Systems, is to evaluate proprietary FPGA technology developed by Achronix Semiconductor Corporation and its effectiveness using a 128-bit, one clock cycle multiplier in a finite field, GF(2128), as a test application. The testing will determine if there is a significant increase in speed that can be achieved by simple modifications of existing synchronous HDL designs using three metrics: number of LUTs, number of registers, and clock speed. Acknowledgements This project set out from the beginning with high hopes and expectations, none of which could have been accomplished without the continued support from our colleagues at General Dynamics C4 Systems and Worcester Polytechnic Institute, who provided unending support that allowed us to complete this Major Qualifying Project. We would like to thank Brendon Chetwynd for the training he provided to us during the busy hours of his work day. We would also like to thank Gerardo Orlando for his explanations into the details that were required to synthesize and code this project correctly and Evan Custodio, a previous MQP student who participated at GDC4S, who provided us with contact information and helped us work through software difficulties. The Achronix Corporation was also kind enough to send Scott Erik Norrholm to the GDC4S site to provide us with a training session in use of the Achronix CAD Environment as well as explain some of the disclosable workings regar