在线可编程技术笔试选题—(答案—题目).docVIP

宁波大学科学技术学院 made in 501 EDA FPGA VHDL程序 -----------------------T1----------------------- library ieee; use IEEE.STD_LOGIC_ARITH.ALL; ENTITY wav_gen is port(clk: IN STD_LOGIC; to_DA:out std_logic_vector(9 downto 0) ); END wav_gen; ARCHITECTURE archi OF wav_gen IS component lcnt is port (clock: in std_logic; q: out std_logic_vector (9 downto 0)); end component; component lrom is port (address: in std_logic_vector (9 downto 0); q: out std_logic_vector (9 downto 0)); end component; begin signal cou_add: std_logic_vector(9 downto 0); U1:lcnt port map(clk,cou_add); U2:lrom port map(cou_add,to_DA); end architecture archi; ----------------------T2---------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY adder4b IS PORT(CIN:IN STD_LOGIC; A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); S:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT:OUT STD_LOGIC); END ENTITY adder4b; ARCHITECTURE BEHAV OF adder4b IS SIGNAL SS,AA,BB:STD_LOGIC_VECTOR(4 DOWNTO 0); BEGIN AA=0A; BB=0B; SS=AA+BB+CIN; S=SS(3 DOWNTO 0); COUT=SS(4); END ARCHITECTURE BEHAV; -----------------------T3--------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use IEEE.STD_LOGIC_ARITH.ALL; ENTITY f_adder is port(ain,bin,cin: IN STD_LOGIC; cout,sum: out std_logic ); END f_adder; ARCHITECTURE archi OF f_adder IS component H_ADDER is port(a,b: in std_logic; co,so: out std_logic); component H_ADDER; begin signal co_int1,co_int2,so_int: std_logic_vector(9 downto 0); U1:H_ADDER port map(ain,bin,co_int1,so_int); U2:H_ADDER port map(so_int,cin,co_int2,sum); cout=co_int1 and co_int2; end architecture archi; --------------------T4----------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MUX_if IS PORT(SEL,AIN,BIN:IN STD_LOGIC_VECTOR(1 DOWNTO 0); COUT:OUT STD_LOGIC_VECTOR(1 DOWNTO 0) END ENTITY MUX_if; ARCHITECTURE BEHAV OF MUX_if IS SIGNAL CC:STD