串行FLASH配置芯片(EPCS1或EPCS4)数据手册.pdfVIP

串行FLASH配置芯片(EPCS1或EPCS4)数据手册.pdf

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串行FLASH配置芯片(EPCS1或EPCS4)数据手册

March 2003, ver. 1.1 Data Sheet Serial Configuration Devices (EPCS1 EPCS4)Features ■ 1- and 4-Mbit flash memory devices that serially configure CycloneTM FPGAs■ Easy-to-use four-pin interface■ Low cost, low pin count and non-volatile memory■ Low current during configuration and near-zero standby mode current ■ 3.3-V operation■ Available in 8-pin small outline integrated circuit (SOIC) package ■ Enables the Nios? processor to access unused flash memory through active serial (AS) memory interface■ Re-programmable memory with more than 100,000 erase/program cycles■ Programming support with ByteBlasterTM II download cable■ Additional programming support with the Altera? Programming Unit (APU) and programming hardware from BP Microsystems, System General, and other vendors ■ Software design support with the Altera Quartus? II development system for Windows-based PCs as well as Sun SPARC station and HP 9000 Series 700/800■ Delivered with the memory array erased (all the bits set to 1) Figure 1 shows the Altera serial configuration device 8-pin SOIC package and its pin-out diagram. Figure 1. Altera Serial Configuration Device Package Pin-Out Diagram 1 Whenever the term “serial configuration device(s)” is used in this document, it refers to Altera EPCS1 and EPCS4 devices. V CC V CC DCLK ASDI V CC GND nCS DATA EPCS1 or EPCS4 Device 1 2 3 4 8 7 6 5Altera Corporation 1 DS-CYCONFIG-1.1 Serial Configuration Devices (EPCS1 EPCS4) Data SheetFunctional Description With SRAM-based devices such as Cyclone FPGAs, configuration data must be reloaded each time the system initializes, or when a new configuration is needed. Serial configuration devices are flash memory devices with a serial interface that can store configuration data for a Cyclone device and reload the data to the device upon power-up or reconfiguration. Table 1 lists the serial configuration devices. Table 2 lists the serial configuration device used with each Cyclone FPGA and the configuration file

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