用VHDL语言数字钟的设计.docVIP

用VHDL语言数字钟的设计 --秒模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity second is port(clk,reset,setmin:in std_logic; daout:out std_logic_vector(6 downto 0); enmin:out std_logic); end second; architecture behav of second is begin process(clk,reset) variable secout:std_logic_vector(6 downto 0); variable min_in: std_logic; begin if clkevent and clk=1 then if resent=1then secout:=0000000; elseif secout(3 downto 0)=1001then secout(3 downto 0):=0000; secout(6 downto 4):=secout(6 downto 4)+1; else secout(3 downto 0):=secout(3 downto 0)+1; end if; if secout=1100000 then secout:=0000000; min_in:=1; else min_in:=0; end if; end if; if setmin=1then min_in:=clk; end if; daout=secout; enmin=min_in; end process; end behav; --分模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity minute is port(enmin,reset,sethour,clk:in std_logic; daout:out std_logic_vector(6 downto 0); enhour:out std_logic); end minute; architecture behav of minute is begin process(enmin,reset) variable minout:std_logic_vector(6 downto 0); variable hour_in:std_logic; begin if enminevent and enmin=1 then if reset=1 then minout:=0000000; elsif minout(3 downto 0)=1001 then minout(3 downto 0):=0000; minout(6 downto 4):=minout(6 downto 4)+1; else minout(3 downto 0):=minout(3 downto 0)+1; end if ; if minout=1100000 then minout:=0000000; hour_in:=1; else hour_in:=0; end if; end if; if sethour=1then hour_in:=clk; end if; daout=minout; enhour=hour_in; end process; end behav; --小时模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hour is port(enhour,reset:in std_logic; daout:out std_logic_vector(5 downto 0)); end hour; architecture behav of hour is begin process(enhour,reset) variable hourout:std_logic_vector(5 downto 0); begin if enhourevent and enhour=1 then if reset=1 then hourout:=000000; elsif hourout(3 downto 0)=1001 then hourout(3 downto 0):=0000; hourout(5 downto 4):=hourout(5 downto 4)+1; els