1_5V0_35_mCMOS3_2Gb_s1_4分接器设计.pdfVIP

41 上 海 交 通 大 学 学 报 Vol. 41 Sup. 2007 4 JOURNAL OF SHANGH AI JIAOT ONG UNIVERSITY Apr. 2007 : 2007) S002404 1. 5 V 0. 35 m CM OS 3. 2 Gb/ s 1 4 邱 玲, 冯 军 ( , 2100 6) : 采用CSM 0. 35 m CM OS 工艺, 设计了低电压高速14 分接器. 分接器采用半时钟树型 构, 由1 个高速12 分接器和2 个低速1 2分接器级联而成. 整个电路实现的基本单元为共栅 动态负载锁存器. 电路最高可工作在 3. 2 Gb/ s, 电源电压为1. 5 V, 整体电路功耗约为120 mW, 芯 片面积为0. 675 mm 0. 675 mm. : 分接器; 低电压; CM OS; 动态负载 : TN 4 2 : A Designof 1.5 V 3.2 Gb/ s Demultiplexer in0.35 mCMOS Process QI U L i ng , FEN G J un ( Inst. of RF OEICs, Southeast Univ. , Nanjing 2100 6, China) Abstract: U sing treetype structure, a low voltage and high speed 1 4 demultiplexer ( DEMU X) based on CSM 0. 35 m CMOS process w as presented. It is made of a highspeed 1 2 DEMU X and tw o parallel lowspeed DEMU X. This circuit employs the commongate dynamicloading latch as its basic cell. The simulation result show s the highest w orking rate can be up to 3. 2 Gb/ s on 1. 5 V supply, with a total pow er consumption of about 120 mW. T he chip size is 0. 675 mm 0. 675 mm. Key ords: demultiplexer ; low voltage; complementary metaloxide semiconductor ( CM OS) ; dynamic loading , 2. 5 V[ 1] , 0. 35 m CM OS , 2 V. . 1. 5 V, , STM 16 . 1 , . CM OS 1. 1 , CM OS , . , . , , STM 16 0. 25 m CMOS . 0. 35 m CMOS , 3. 3 V | Utp | = 0. 84 V, Utn = 0. 6 V, : : ( 1 82) , ,, , , Email: qiuling seu@ 126. com . - ( ) , , , ,Email: fengjun seu@ seu . edu. cn. - 邱 玲, 等: 1. 5 V 0. 35 m CM OS 3. 2 Gb/ s 1 4 分接器设计