COA课件16.ppt

William Stallings Computer Organization and Architecture6th Edition Chapter 16 Control Unit Operation 控制器的操作 ※§16.1 Micro-Operations 微操作 A computer executes a program —Fetch/execute cycle Each cycle has a number of steps Called micro-operations —μops Symbolic representation of information flow Each step does very little Atomic(基本的或原子的) operation of CPU Micro-operations include A transfer between registers A transfer between a register and an external interface A simple arithmetic or logic operation Constituent Elements of Program Execution Four Registers They are essential to instruction execution Memory Address Register (MAR) — Connected to address bus — Specifies address for read or write in memory Memory Buffer Register (MBR) — Connected to data bus — Holds data to write to or read from memory Program Counter (PC) 程序计数器 — Hold address of next instruction to be fetched Instruction Register (IR) — Hold the last instruction fetched 1. Fetch Sequence Address of next instruction is in PC Address (MAR) is placed on address bus Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR PC incremented by 1 (in parallel with data fetch from memory) Data (instruction) moved from MBR to IR MBR is now free for further data fetches See page422 figure12.6 Information Flow (Fetch Diagram) Fetch –T1 Fetch –T2 Fetch –T3 Fetch –T4 Fetch Sequence (symbolic) t1: (PC) - MAR t2: (MAR) Memory by address bus read Memory by control bus t3: Memory MBR by data bus t4: (MBR) - IR (PC) +1 - PC (Maybe happen in t2,t3 and t4) (tx = time unit/clock cycle) Rules for Clock Cycle Grouping (1) Proper sequence must be followed* MAR - (PC) must precede MBR - Memory (2) Conflicts must be avoided* Must not read write same register at same time MBR - Memory IR - (MBR) must not be in same cycle Also: PC - (PC) +1 involves addition Use ALU