1553B总线接口电路存储器管理控制系统设计.pdfVIP

Subject : Design of RAM Management and Control System in 1553B Data Bus Interface Circuit Specialty : Microelectronics and Solid State Electronics Name : He Zhenzhen (Signature) Instructor: Zhu Xiangdong (Signature) ABSTRACT MIL-STD-1553B is a centralized control and Time Division Command/Response Multiplex Data Bus military standard, it has been widely applied in avionics systems because of its advantages of good topology, high speed and high reliability. It also made great contributions to the development of integrated avionics system. The key of 1553B bus system is bus interface circuit, but, at present domestic design and production technology of 1553B bus interface circuit is not mature enough, and most of them are imported from foreign companies. So the independent research of 1553B bus interface circuit is of great significance and value for china. 1553B bus interface circuit mainly consists of transceivers, Manchester encoding and decoding, 1553B protocol processor and shared memory. It can complete all functions in BC, RT and MT mode. Shared memory stores all data transmitted between the terminal subsystem and the data bus, these data are based on certain message format for transmission. In different mode, the shared memory message processing is different, so the shared memory storage and management mechanism is different, and the memory read and write logic is also different. With the expanding of 1553B bus application filed, 1Mbps data transfer rate does not meet the needs of all users, so 1553B bus interface design is also developing to high-speed. Based on the detailed studying of the MIL-STD-1553B d