PI基础知识及PDN设计剖析.ppt

* * * * * * * * (1,0) mode. Standing wave formed along the longer side. (1,1) mode. We need to satisfy boundary conditions along both the x and y sides * * * * * * * * * * * 目标阻抗50毫欧。 * * * * Istvan Novak PDN元件 芯片 目前芯片和芯片封装的内部特性对用户很少公开，给PCB的PDN设计造成一定困扰 解决的途径： 器件手册、参考设计 来自于芯片厂家的统计数据 参考业界的设计经验 PDN元件 芯片内的PDN 芯片封装电感使PCB上的去耦电容在高频的作用弱化 芯片bonding线电感使封装上去耦电容在甚高频的作用弱化 频率大于1GHz由芯片的去耦电容起作用 PDN元件 芯片封装电感 芯片封装电感 PDN元件 芯片电容 芯片电容 PDN测试 电源噪声的时域测试 示波器20M 带宽测试， 主要测试VRM性能 示波器500M 带宽测试，主要测试PDN去耦效果 PDN的频域测试 原理图和PCB设计时放置好PI测试点 PI测试点的原理图库：$LIB\standard\tp1x2 选tp1x2_1 PDN设计总结 根据最大负载电流，做好电源路径的载流能力设计 根据芯片的要求和应用确定目标阻抗 根据DC和低频性能，选择合适的VRM 设计偏保守的去耦网络满足目标阻抗要求 足够的电容容量来满足低频段的目标阻抗 实用的低安装电感的布线方式让去耦电容有好的高频性能 优化PCB的叠板 量化电容的规格和数量，降低反谐振点的阻抗 实测电源噪声确保设计符合要求 参考资料 Howard Johnson 《高速数字设计》 * * * * * * * Assuming the reference is a fixed offset above GND, the voltage received at the input of the differential amplifier is: Any noise voltage between the GND terminals of GA and GC adds to the incoming signal voltage and reduces the noise margin for GC. * Low GND inductance alone does not solve the common-path noise problem Impedance between power pins should be just as low as impedance between GND pins. ?Also note that the impedance of the battery must also be very low to maintain stable transmitted signal levels. Here, the only path is through the battery -- in real systems, there are other paths, either way, there MUST exist a low impedance path between PWR and GND. In the Hi states,a gate’s output voltage depends on the voltage at its power terminal. Any changes in the power voltage,caused by returning signal currents flowing in the power wiring/Plane,directory affect the output voltage. * Any system that satisfies these three power system design rules will: Provide a stable reference voltage Have a low common-path noise Maintain a uniform power distribution voltage everywhere These are inseparable -- helping one property will generally help others. B