ASIC_Design_Chip_IO_Design芯片IO设计概要1.ppt

I/O PADS In, Out , InOut , Gnd , Vdd, Source follower Bidirectional Pad -Digital Component. Pad Layout Pad In DC Analysis Max frequency 100Mhz Pad out Dc Analysis Max frequency 30Mhz with 10pF capacitor as load Sf with no ideal current source SF Layout SF behavior (with the pmos as current source) Slew Rate of the SF Pad I/O With ESD PadIOEsd Layout Modeling the Pad The modeling was done by attaching a capacitor, and a resistor, to the pad. They reperesent the capacitance and resistance of three main models: Human, machine, and package. Human model. Machine Model. Package Model * * Operates as Pad_in or Pad_out: EO high = pad out. EO low = pad in. DataIn OE DataOut DataInUnBuf DataInBuf DataInB, after one inverter, has less gain than dataIn Dx = 4.11nsec (80%*5=4nsec) Cursers mark position where output exceed 80% of max input value VinBar Vin Vpad Response similar to dataIn. Explanation: It has two levels of amplifying, as the dataIn node. Vpad DataOut Dx = 14.06nsec ( 80%*17=13.6nsec) Cursors mark position where output exceed 80% of max input value Function: Pad follows Signal, with DC offset. Signal Vdd Vss Current source values -190 to -150 uA 0Vin4 volt, the SF follow the input with 0.85 V offset. 3.5V 4 V Let’s have a closer look Vpad – Vsignal = 0.85 constant when 0 Vsignal = 4 Vsignal Vpad Vpad-Vsignal Vsignal = ramp from 0 to 5v in 1usec The SF still follow the step in the range of 0VSignal4volt Two diodes are placed to protect the chip, and are normally at reverse charge. When signal exceeds 5+Vb volts, then D2 is forward biased and discharges the excess voltage. When signal is below –Vb, then a similar discharging process occurs through D1. D2 D1 Diode 1 ?D1 in schematic Diode 2 ? D2 in scehematic signal To run simulation, an initial voltage was initialized on the model. R=1.5kΩ, C=100pF, Initial Voltage = 2kV *