天津大学数字集成电路第三讲反相器.ppt

* dc points located at the intersection of the corresponding load lines Note all operating points are located either at the high or low output levels * For lecture VTC of the inverter exhibits a very narrow transition zone; high gain during switching transient (when both PMOS and NMOS are simultaneously on and in saturation). In that region, a small change in input voltage results in a large output voltage variation. Indicate on VTC plot where VTn and VTp lie * For class. response determined mainly by the output capacitance of the gate, CL - drain diffusion capacitance of the NMOS and PMOS transistors; the connecting wires, and the input capacitances of the fan-out gates A fast gate is built either by keeping the output capacitance small or by decreasing the on-resistance or the transistor (or both) Decreasing the on-resistance achieved by increasing the W/L ratio of the device Be award that the on-resistance of the NMOS and PMOS transistors is not constant; rather it is a nonlinear function of the voltage across the transistor * A high gain in the transition region is VERY desirable. In the extreme case of an infinite gain, the noise margins simplify to VOH – VM and VM – VOL for NMH (ideally, VDD – VM) and NML (ideally, VM – GND), respectively, and span the complete voltage swing. * Note: simulation overestimates the gain – as seen on the next slide, the maximum gain (at VM) is only -17 And piece-wise linear approximation model is optimistic wrt noise margins. Low output resistance is a good measure of the sensitivity of the gate wrt noise induced at the output and should be as low as possible. * A good device has a small oxide thickness (-3nm), a small length (-25nm), a higher width (+30nm) and a smaller threshold (-60mV). The opposite is true for a bad device. * Not the best curve for 0.5 supply (but the best I could do in ppt). Observations The gain of the inverter in the transition region increases with a reduction in Vdd. For a fixed r, VM is pr