基于部分积优化的高速并行乘法器实现-西安电子科技大学.PDF

28 1 V ol . 2 8 N o. 1 2011 1 MICROEL ECT R ON ICS COM PU T ER J anuar y 2011 李 康, 林钰凯, 马佩军, 史江义, 梁 亮 ( , 7 1007) : 提出了部分积产生与压缩单元的改进结构, 过对部分积产生算法进行优化, 采用选择器结构来替换传统 的与或门, 提高了部分积电路的性能, 并降低了该模块的面积与功耗. 对压缩单元的优化提高了部分积压缩的速 度. 对16 16 并行乘法器综合验证表明, 改进的乘法器性能提高 14 . 5% , 面积减少7 . 1% , 同时功耗下降17. 2% . : 数字信号处理 乘法器电路 编码 低功耗 : T N47 : A : 1000- 7 180( 2011) 01- 00 61- 03 Implementation of Highspeed Parallel Multiplier Based on Optimized Partial Product L I Kang , L IN Y ukai , M A Peijun , SH I Jiangyi , L IA N G L iang ( Key Labor ator y w ide Bandg ap Sem ico ndu cto r M at erial s and Device, Xidian U niver sity, Xi an 710071, China) Abstract: A n impr oved architecture o f par tial pr oduct g ener ation and co mpr essing unit s is researched in t his pap er. By o pt im izing the p artial pro du ct generating alg or ithm w ith multiplex ers in stead of tr aditio nal AN D and O R gat es, the p erf o rm ance o f p artia l produ ct circu it s is impro ved . M eanw hile, the ar ea and po w er co nsumpt ion of the module is also decreased. Optim ized compresso r unit s enh ance the sp eed of par tial pr oduct compression pr ocessing . T he re sult s of synthesis and v erif ication f or 16 16 p ara llel multiplier show th at it s p erf o rm ance w as incr eased by 14. 5% , as w ell as the ar ea decreased by 7. 1% and the pow er con sumptio n redu ced by 17. 2% . Key words: dig ital sig nal pr ocessing multiply ing cir cuit s enco ding lowpo w er electro nics 4 Boo th , 1 . :