Chip Scale Package (CSP) Wire Bonding （芯片规模包(CSP)引线结合）.pdf

Chip Scale Package (CSP) Wire Bonding Capability Study Rufino Ringor ST Assembly and Test Services Pte. Ltd. 5 Yishun Street 23 Sin gap ore 768442 Jimmy Castaneda SPT Asia Pte. Ltd. 970 Toa Pay oh North #07-25/26 Singap ore 318992 Abstract : t o t est at high speed and burn-in for known good die (KGD), to handle, to assemble, to The emergence of the new advanced package rework , to st andardize, to protect the die, t o t echnology chip scale package (CSP ) in the deal with die shrink and expand, and it is semiconductor industry has been increasingly subj ect to less infrastructure constraint s.1 The becoming popular. In this study , the focus CSP construct ion and size makes suit able for will be made on the CSP package types using high lead count I/O (up t o 1200). wire bonding int erconnect t echnology , which was performed t o det ermine the degree of The present assembly infrastructure (e.g. wire limit at ion and challenges of having a short and bond equipment , et c...) has matured over the low looping profile as dict at ed by the years. Changing from one packaging allowable CSP package thickness. T wo maj or t echnology int o another means new resources considerat ions were studied and invest igat ed, and investment . Given this scenario, the namely : the short and low wi