数字集成电路 digitalic06lyn传输管逻辑.ppt

EE141 * EE141 * EE141 * EE141 * EE141 * For lecture Evaluate transistor, Me, eliminates static power consumption EE141 * This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails. EE141 * CL being lower also contributes to power savings EE141 * CL being lower also contributes to power savings EE141 * CL being lower also contributes to power savings EE141 * leakage sources are reverse-biased diode and the sub-threshold leakage of the NMOS pulldown device. Charge stored on CL will leak away with time (input in low state during evaluation) Requires a minimum clock rate - so not good for low performance products such as watches (or when have conditional clocks) PMOS precharge device also contributes some leakage due to reverse bias diode and subthreshold conduction that, to some extent, offsets the leakage due to the pull down paths. EE141 * During precharge, Out is VDD and inverter out is GND, so keeper is on During evaluation if PDN is off, the keeper compensates for drained charge due to leakage. If PDN is on, there is a fight between the PDN and the PUN - circuit is ratioed so PDN wins, eventually Note Psc during switching period when PDN and keeper are both on simultaneously EE141 * CA initially discharged and CL fully charged. EE141 * EE141 * Out = A xor B xor C What is the worst case change in voltage on node Out - assume all inputs are low during precharge and all internal capacitances are initially 0V Worst case is obtained by exposing the maximum amount of internal capacitance to the output node during evaluation. This happens when !A B C or A !B C 30/(30+50) * 2.5 V = 0.94 V so the output drops to 2.5 - 0.94 = 1.56 V EE141 * EE141 * Due to capacitive backgate coupling between the internal and output node of the static gate and the output of the dynamic gate, Out1 voltage reduces EE141 * Out1 overshoots Vdd (2.5V) due to clock feedthrough And Out2 never