characterization of defect traps in sio2 thin films描述缺陷陷阱的二氧化硅薄膜.pdfVIP

Active and Passive Elec. Comp., 2001, Vol. 24, pp. 169 -175 () 2001 OPA (Overseas Publishers Association) N.V. Reprints available directly from the publisher Published by license under Photocopying permitted by license only the Gordon and Breach Science Publishers imprint, member of the Taylor Francis Group. CHARACTERIZATION OF DEFECT TRAPS IN SiO THIN FILMS JEAN-YVES ROSAYEa, PIERRE MIALHEb, JEAN-PIERRE CHARLESc, MITSUO SAKASHITAa, HIROYA IKEDAa, AKIRA SAKAIa, SHIGEAKI ZAIMAa, YUKIO YASUDAa Department of Crystall#te Materials Science, Graduate School ofEngineer#tg, Nagoya University, Furo-cho, Chikusa-ku, Nagoya-city, 464-8603, Japan; bSemiconductor Physics, Department of Fundamental Researches, Perpignan University, 52 avenue de Villeneuve, 66860 Perpignan Cedex, France; CMOPS-CLOES-SUPELEC, Metz University, 2 rue Edouard Belin, 57070 Metz, France; Center for Cooperative Research on Advanced Science and Technology, Nagoya University, Furocho, Chikusa-ku, Nagoya-city, 464-8603, .Japan (Received3 April 2001; In final form 15 May 2001 In order to understand the degradation of the electrical operations of metal-oxide- semiconductor (MOS) devices, this work is concerned by the defects generation processes in the non-stoichiometric SiO, area and at the SiO2 interface. For this purpose, a new measurement technique to study slow-state traps and their relationship with fast-state traps is developed. This method considers capacitance- voltage measurements and temperature effects during the hysteresis cycle. Keywords: Gate oxide; MOS capacitor; C-V characteristics; Hysteresis; Slow-state traps; Defects 1. INTRODUCTION Under normal operating condition, interface states and oxide defects are generated