scaling of phemts to decanano dimensions缩放phemts decanano维度.pdfVIP

VLSI DESIGN (C) 2001 OPA (Overseas Publishers Association) N.V. 2001, Vol. 13, Nos. 1-4, pp. 435-439 Published by license under Reprints available directly from the publisher the Gordon and Breach Science Publishers imprint, Photocopying permitted by license only member of the Taylor Francis Group. Scaling of pHEMTs to Decanano Dimensions K. KALNA*, A. ASENOV, K. ELGAID and I. THAYNE Device Modelling Group, Department ofElectronics and Electrical Engineering, University of Glasgow, Glasgow G12 8LT, Scotland, United Kingdom The effect of scaling into deep decanano dimensions on the performance of pseudo- morphic high electron mobility transistors (pHEMTs) is extensively studied using Monte Carlo simulations. The scaling of devices with gate lengths of 120, 70, 50 and 30nm is performed in both lateral and vertical directions. The devices exhibit a significant improvement in transconductance during scaling, even though external resistances become a limiting factor. Keywords: pHEMT; Monte Carlo simulation; Scaling; Roadmap; Transconductance 1. INTRODUCTION strain relief buffers [3, 4]. The GaAs substrate is still much cheaper, more manufacturable and has Pseudomorphic high electron mobility transistors a large accessible scale of strain in comparison (pHEMTs)with low indium content channels and with the InP subst