硬件乘除法运算器设计.docVIP

硬件乘除法运算器设计 设计题目：位数自己定，包含键盘输入，LED数码管输出显示 一、4*4矩阵键盘编码器中各模块设计 1.1分频器fdiv设计 library ieee; use ieee.std_logic_1164.all; entity fdiv is generic(n:integer :=50000); port(rst:in std_logic; clkin:in std_logic; clkout:out std_logic); end fdiv; architecture a of fdiv is signal cnt:integer range 0 to n; begin process(clkin,rst) begin if rst=0 then cnt=0;clkout=0; elsif clkinevent and clkin=1 then if cnt=n-1 then cnt=0;clkout=1; else cnt=cnt+1;clkout=0; end if; end if; end process; end a; 1.2键盘扫描scan设计 library ieee; use ieee.std_logic_1164.all; entity scan is port(keyin:in std_logic_vector(3 downto 0); clk,en:in std_logic; keyout:out std_logic_vector(3 downto 0); key_press:out std_logic); end scan; architecture a of scan is signal cnt:integer range 0 to 3; begin process(clk) begin if clkevent and clk=1 then if en=1 then if cnt=3 then cnt=0; else cnt=cnt+1; end if; end if; end if; end process; process(cnt) begin case cnt is when 0=keyout=1110; when 1=keyout=1101; when 2=keyout=1011; when 3=keyout=0111; when others=keyout=1111; end case; end process; key_press=keyin(3) and keyin(2) and keyin(1) and keyin(0); end a; 1.3按键编码器key-decode设计 library ieee; use ieee.std_logic_1164.all; entity key_decode is port(keyout:in std_logic_vector(3 downto 0); keyin:in std_logic_vector(3 downto 0); key4:out std_logic_vector(3 downto 0)); end key_decode; architecture a of key_decode is signal key8:std_logic_vector(7 downto 0); begin key8=keyinkeyout; process(key8) begin case key8 is whenkey4=0000; whenkey4=0001; whenkey4=0010; whenkey4=0011; whenkey4=0100; whenkey4=0101; whenkey4=0110; whenkey4=0111; whenkey4=1000; whenkey4=1001; whenkey4=1010; whenkey4=1011; whenkey4=1100; whenkey4=1101; whenkey4=1110; whenkey4=1111; when others=key4=0000; end case; end process; end a; 1.4消抖动计数器qudou设计 library ieee; use ieee.std_logic_