电子系统设计(第1周)PLD概述.pptVIP

Enabling the Highest Growth Megatrends ALL PROGRAMMABLE 5G Wireless n SDN/NFV n Video/Vision n ADAS n Industrial IoT n Cloud Computing Page * PLD Market Share - Calendar Year 2014 Source: IHS iSuppli March 2015 With ~50% Market Share, Xilinx is the #1 PLD Supplier Xilinx 49% Altera 38% Others 13% Zynq-7000 All Programmable SoC Zynq in Academia Zybo Zynq Book ZedBoard PLD设计方法的演变 Equations Schematics Synthesis Macrofunctions Second-Generation Synthesis IP Megafunctions Block-Based Design Increasing Time-to-Market Pressures Drive Change 主要PLD设计开发环境 PLD公司 Altera Quartus II Xilinx Vivado/ISE 专业EDA公司（第三方工具） Cadence Synopsys Mentor Graphics 主要PLD设计开发环境界面举例 PLD设计开发流程 基于PLD的系统开发工作 软件开发方面 设计输入 原理图或硬件描述语言 设计校验 设计编译 包括布局布线、生成流文件、时序仿真分析、底层设计分析等 配置和下载 硬件开发方面（PCB） 供电与配置口连接 I/O定义 本次授课内容主要问题回顾 如何理解“全硬件编程” 本次授课内容主要问题回顾 PLD与ASIC两种产品设计方案各自有哪些优缺点？ PLD与MCU的设计和应用有哪些差异？ 谈谈CPLD与FPGA的区别并以产品为例进行说明。 简述MAX II系列芯片的构架和特点。 简要介绍PLD设计流程。 本次授课内容主要问题回顾 授课时出现的主要技术名词缩写 PLD ASIC CPLD FPGA MCU DSP LUT LE ISP EDA SOPC VLSI HDL JTAG PS * “Time to Market”、“Digital Era” * In the last year we have rolled out key foundational elements; Complemented Vivado HLS software defined hardware with 3 SDx software defined development environments Launched the industry’s first All Programmable Zynq MPSoC with 7 software programmable embedded processors Launched 2 generations of UltraScale ASIC-class FPGAs and 3D ICs * Building on the success of the dual-A9 core Zynq-7000 family, the Zynq UltraScale+ MPSoC family delivers a step function in capability to meet the demand for higher performance, greater processing capability and specific processing engines for specific application tasks. It also addresses the need to balance performance with system power by leveraging the performance-per-watt characteristics of FinFET and unprecedented levels of programmable systems integration to