计算机系与统结构 分级存储器体系 .ppt

Cache Q3: Which Block Should Be Replaced on a Cache Miss? When a miss occurs, the cache controller must select a block to be replaced with the desired data. A benefit of direct-mapped placement is that hardware decisions are simplified – in face, so simple that there is no choice: Only one block frame is checked for a hit, and only that block can be replaced. With fully associative or set-associative placement, there are many blocks to choose from on a miss. There are three primary strategies employed for selecting which block to replace: Cache Q3: Which Block Should Be Replaced on a Cache Miss? Data cache misses per 1000 instructions 92.5 92.1 92.1 92.5 92.1 92.1 92.5 92.1 92.2 256 KB 100.3 100.5 99.7 103.1 102.3 102.4 103.9 104.3 103.4 64 KB 110.4 111.8 109.0 113.3 115.1 111.7 115.5 117.3 114.1 16 KB FIFO RAM LRU FIFO RAM LRU FIFO RAM LRU Size Eight-way Four-way Two-way 　 Associative There is little difference between LRU and random for the largest size cache LRU outperforming the others for smaller caches. FIFO generally outperforms random in the smaller cache sizes. Cache Q4: What Happens on a Write? Read cache: The block can be read from the cache at the same time that the tag is read and compared, so the block read begins as soon as the block address is available. . If it is hit, the requested part of the block is passed on to the CPU immediately . If it is a miss, just ignore the value read. Modifying a block cannot begin until the tag is checked to see if the address is a hit. Because tag checking cannot occur in parallel, writes normally take longer than reads. Cache Q4: What Happens on a Write? There are two basic options when writing to the cache: Write through – The information is written to both the block in the cache and to the block in the lower-level memory. Write back – The information is written only to the block in the cache. The modified cache block in written to main memory on