电子EDA复习资料（五邑大学）程序.docVIP

模10： module count10(out,cout,en,clr,clk); input en,clr,clk; output[3:0] out; output cout; reg[3:0] out; always @(posedge clk or posedge clr) begin if(clr) out=0; else if(en) begin if(out==9) out=0; else out=out+1; end end assign cout=((out==9)en)?1:0; endmodule module fre_ctrl(clk,rst,count_en,count_clr,load); input clk,rst; output count_en,count_clr,load; reg count_en,load; always @(posedge clk) begin if(rst) begin count_en=0;load=1; end else begin count_en=~count_en; load=~count_en; end end assign count_clr=~clkload; endmodule module latch_24(q0,din,load); input load;input[23:0] din; output [23:0] q0;reg[23:0] q0; always @(posedge load) begin q0=din;end endmodule 4： module zifuxs(clr,clk,a,b,c,d,e,f,g,w); input clr,clk; //定义输入变量 output a,b,c,d,e,f,g,w; //定义输出变量 reg[3:0] out; //定义中间变量 reg a,b,c,d,e,f,g,w; always @(posedge clk or posedge clr) begin if(clr) out=0; //异步清零 else begin if(out==15) out=0; else out=out+1; end end always @(out[3:0]) begin case(out[3:0]) //用case语句进行译码 4h0:{a,b,c,d,e,f,g,w}=7b1111110; 4h1:{a,b,c,d,e,f,g,w}=7b0110000; 4h2:{a,b,c,d,e,f,g,w}=7b1101101; 4h3:{a,b,c,d,e,f,g,w}=7b1111001; 4h4:{a,b,c,d,e,f,g,w}=7b0110011; 4h5:{a,b,c,d,e,f,g,w}=7b1011011; 4h6:{a,b,c,d,e,f,g,w}=7b1011111; 4h7:{a,b,c,d,e,f,g,w}=7b1110000; 4h8:{a,b,c,d,e,f,g,w}=7b1111111; 4h9:{a,b,c,d,e,f,g,w}=7b1111011; 4ha:{a,b,c,d,e,f,g,w}=7b1110111; 4hb:{a,b,c,d,e,f,g,w}=7b0011111; 4hc:{a,b,c,d,e,f,g,w}=7b1001110; 4hd:{a,b,c,d,e,f,g,w}=7b0111101; 4he:{a,b,c,d,e,f,g,w}=7b1001111; 4hf:{a,b,c,d,e,f,g,w}=7b1000111; default:{a,b,c,d,e,f,g,w}=7bx; //当值不为上述时输出bx endcase w=1; end endmodule module xljcq(x,z,clk,reset,state); input x,clk,reset; output z; output[2:0] state; reg[2:0] state; reg z; parameter s0=3b000, //定义变量s0、、、s7 s1=3b001, s2=3b010, s3=3b011, s4=3b100, s5=3b101, s6=3b110, s7=3b111; always @(posedge clk) //敏感信号为边沿触发clk beg