论文-基于CPLD的高速数据采集系统.docVIP

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  • 约2.01万字
  • 约 43页
  • 2017-11-22 发布于四川
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摘 要 本文针对高速数据采集的设计,介绍高速数据采集卡的硬件结构及工作原理,讲述CPLD在数据采集与数据存储的VHDL模块设计,给出模块的VHDL源程序用于指导PCB布局、布线约束规则的过程及思路VHDL 高速数据采集卡 ABSTRACT This paper is about the high-speed data acquisition card. It will describes the hardware structure and working principle of the high- speed acquisition card , and the VHDL module design on CPLD about the time series control on data collection and data store. It will also show all of the program lists. In this article, it will analyses some problem of the high-speed circuits. It will discuss the method of PCB wir

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